CD74HC4015 高速 CMOS 逻辑双向 4 级静态移位寄存器

The ’HC4015 consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent Clock (CP) and Reset (MR) inputs as well as a single serial Data input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive- going clock transition. Resetting of all stages is accomplished by a high level on the reset line.

The device can drive up to 10 low power Schottky equivalent loads. The ’HC4015 is an enhanced version of equivalent CMOS types

CD74HC4015
Technology Family HC
Rating Catalog  
CD74HC4015 特性
CD74HC4015 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
CD74HC4015E ACTIVE -55 to 125 0.39 | 1ku PDIP (N) | 16 25 | TUBE CD74HC4015E
CD74HC4015EE4 ACTIVE -55 to 125 0.39 | 1ku PDIP (N) | 16 25 | TUBE CD74HC4015E
CD74HC4015M ACTIVE -55 to 125 0.42 | 1ku SOIC (DW) | 16 50 | TUBE HC015M
CD74HC4015ME4 ACTIVE -55 to 125 0.42 | 1ku SOIC (DW) | 16 50 | TUBE HC015M
CD74HC4015MG4 ACTIVE -55 to 125 0.42 | 1ku SOIC (DW) | 16 50 | TUBE HC015M
CD74HC4015 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
CD74HC4015E Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type CD74HC4015E CD74HC4015E
CD74HC4015EE4 Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type CD74HC4015EE4 CD74HC4015EE4
CD74HC4015M Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD74HC4015M CD74HC4015M
CD74HC4015ME4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD74HC4015ME4 CD74HC4015ME4
CD74HC4015MG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD74HC4015MG4 CD74HC4015MG4
CD74HC4015 应用技术支持与电子电路设计开发资源下载
  1. CD74HC4015 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)