CY74FCT16500CT 具有三态输出的 18 位通用总线收发器

These 18-bit universal bus transceivers can be operated in transparent, latched, or clock modes by combining D-type latches and D-type flip-flops. Data flow in each direction is controlled by output-enable (OEAB and OEBA\), latch enable (LEAB and LEBA), and clock inputs (CLKAB\ and CLKBA\) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB\ is held at a HIGH or LOWlogic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOWtransition of CLKAB\. OEAB performs the output enable function on the B port. Data flow from B-to-A is similar to that of A-to-B and is controlled by OEBA\, LEBA, and LKBA.

CY74FCT16500CT
Rating Catalog  
Technology Family FCT
CY74FCT16500CT 特性
CY74FCT16500CT 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
74FCT16500CTPACT ACTIVE -40 to 85 1.40 | 1ku TSSOP (DGG) | 56 2000 | LARGE T&R  
74FCT16500CTPVCT ACTIVE -40 to 85 1.50 | 1ku SSOP (DL) | 56 1000 | LARGE T&R  
FCT16500CTPACTE4 ACTIVE -40 to 85 1.40 | 1ku TSSOP (DGG) | 56 2000 | LARGE T&R  
FCT16500CTPACTG4 ACTIVE -40 to 85 1.40 | 1ku TSSOP (DGG) | 56 2000 | LARGE T&R  
FCT16500CTPVCTG4 ACTIVE -40 to 85 1.50 | 1ku SSOP (DL) | 56 1000 | LARGE T&R  
CY74FCT16500CT 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
74FCT16500CTPACT Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 74FCT16500CTPACT 74FCT16500CTPACT
74FCT16500CTPVCT Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 74FCT16500CTPVCT 74FCT16500CTPVCT
FCT16500CTPACTE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM FCT16500CTPACTE4 FCT16500CTPACTE4
FCT16500CTPACTG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM FCT16500CTPACTG4 FCT16500CTPACTG4
FCT16500CTPVCTG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM FCT16500CTPVCTG4 FCT16500CTPVCTG4
CY74FCT16500CT 应用技术支持与电子电路设计开发资源下载
  1. CY74FCT16500CT 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器通用总线功能产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)