SN74ALS112A 具有清零和预设功能的双路 J-K 下降沿触发器

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs, regardless of the levels of the other inputs. When and are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C

SN74ALS112A
Voltage Nodes(V) 5  
Technology Family ALS  
Rating Catalog
SN74ALS112A 特性
SN74ALS112A 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74ALS112AD ACTIVE 0 to 70 0.90 | 1ku SOIC (D) | 16 40 | TUBE ALS112A
SN74ALS112ADE4 ACTIVE 0 to 70 0.90 | 1ku SOIC (D) | 16 40 | TUBE ALS112A
SN74ALS112ADG4 ACTIVE 0 to 70 0.90 | 1ku SOIC (D) | 16 40 | TUBE ALS112A
SN74ALS112ADR ACTIVE 0 to 70 0.75 | 1ku SOIC (D) | 16 2500 | LARGE T&R ALS112A
SN74ALS112ADRE4 ACTIVE 0 to 70 0.75 | 1ku SOIC (D) | 16 2500 | LARGE T&R ALS112A
SN74ALS112ADRG4 ACTIVE 0 to 70 0.75 | 1ku SOIC (D) | 16 2500 | LARGE T&R ALS112A
SN74ALS112AN ACTIVE 0 to 70 0.85 | 1ku PDIP (N) | 16 25 | TUBE SN74ALS112AN
SN74ALS112AN3 OBSOLETE 0 to 70   PDIP (N) | 16    
SN74ALS112ANE4 ACTIVE 0 to 70 0.85 | 1ku PDIP (N) | 16 25 | TUBE SN74ALS112AN
SN74ALS112ANSR ACTIVE 0 to 70 0.85 | 1ku SO (NS) | 16 2000 | LARGE T&R ALS112A
SN74ALS112ANSRE4 ACTIVE 0 to 70 0.85 | 1ku SO (NS) | 16 2000 | LARGE T&R ALS112A
SN74ALS112ANSRG4 ACTIVE 0 to 70 0.85 | 1ku SO (NS) | 16 2000 | LARGE T&R ALS112A
SN74ALS112A 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74ALS112AD Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ALS112AD SN74ALS112AD
SN74ALS112ADE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ALS112ADE4 SN74ALS112ADE4
SN74ALS112ADG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ALS112ADG4 SN74ALS112ADG4
SN74ALS112ADR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ALS112ADR SN74ALS112ADR
SN74ALS112ADRE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ALS112ADRE4 SN74ALS112ADRE4
SN74ALS112ADRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ALS112ADRG4 SN74ALS112ADRG4
SN74ALS112AN Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type SN74ALS112AN SN74ALS112AN
SN74ALS112ANE4 Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type SN74ALS112ANE4 SN74ALS112ANE4
SN74ALS112ANSR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ALS112ANSR SN74ALS112ANSR
SN74ALS112ANSRE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ALS112ANSRE4 SN74ALS112ANSRE4
SN74ALS112ANSRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ALS112ANSRG4 SN74ALS112ANSRG4
SN74ALS112A 应用技术支持与电子电路设计开发资源下载
  1. SN74ALS112A 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)