SN74AUC1G74 具有清零和预设功能的双路上升沿 D 类触发器

This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR input overrides the PRE input when they are both low.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down

SN74AUC1G74
Pin/Package 8DSBGA, 8SM8, 8UQFN, 8US8
Operating Temperature Range(°C) -40 to 85  
IOL(mA) 9  
IOH(mA) -9  
Vcc max(V) 2.7  
Technology Family AUC  
Vcc min(V) 0.8  
Approx. Price (US$) 0.26 | 1ku  
tpd max(ns) 1.2  
ICC(uA) 10  
Rating Catalog
SN74AUC1G74 特性
SN74AUC1G74 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74AUC1G74DCTR ACTIVE -40 to 85 0.26 | 1ku SM8 (DCT) | 8 3000 | LARGE T&R  
SN74AUC1G74DCTRE4 ACTIVE -40 to 85 0.26 | 1ku SM8 (DCT) | 8 3000 | LARGE T&R  
SN74AUC1G74DCTRG4 ACTIVE -40 to 85 0.26 | 1ku SM8 (DCT) | 8 3000 | LARGE T&R  
SN74AUC1G74DCUR ACTIVE -40 to 85 0.29 | 1ku US8 (DCU) | 8 3000 | LARGE T&R  
SN74AUC1G74DCURE4 ACTIVE -40 to 85 0.29 | 1ku US8 (DCU) | 8 3000 | LARGE T&R  
SN74AUC1G74DCURG4 ACTIVE -40 to 85 0.29 | 1ku US8 (DCU) | 8 3000 | LARGE T&R  
SN74AUC1G74RSER ACTIVE -40 to 85 0.26 | 1ku UQFN (RSE) | 8 3000 | LARGE T&R  
SN74AUC1G74RSERG4 ACTIVE -40 to 85 0.26 | 1ku UQFN (RSE) | 8 3000 | LARGE T&R  
SN74AUC1G74YZPR ACTIVE -40 to 85 0.40 | 1ku DSBGA (YZD) | 8 3000 | LARGE T&R  
SN74AUC1G74 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74AUC1G74DCTR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74AUC1G74DCTR SN74AUC1G74DCTR
SN74AUC1G74DCTRE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74AUC1G74DCTRE4 SN74AUC1G74DCTRE4
SN74AUC1G74DCTRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74AUC1G74DCTRG4 SN74AUC1G74DCTRG4
SN74AUC1G74DCUR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74AUC1G74DCUR SN74AUC1G74DCUR
SN74AUC1G74DCURE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74AUC1G74DCURE4 SN74AUC1G74DCURE4
SN74AUC1G74DCURG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74AUC1G74DCURG4 SN74AUC1G74DCURG4
SN74AUC1G74RSER Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74AUC1G74RSER SN74AUC1G74RSER
SN74AUC1G74RSERG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74AUC1G74RSERG4 SN74AUC1G74RSERG4
SN74AUC1G74YZPR Green (RoHS & no Sb/Br)  SNAGCU  Level-1-260C-UNLIM SN74AUC1G74YZPR SN74AUC1G74YZPR
SN74AUC1G74 应用技术支持与电子电路设计开发资源下载
  1. SN74AUC1G74 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)