SN74GTLPH1612 18 位 LVTTL 到 GTLP 可调节边缘速率通用总线收发器

The SN74GTLPH1612 is a high-drive, 18-bit UBT™ transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models.

SN74GTLPH1612
Voltage Nodes(V) 3.3  
A Side LVTTL  
B Side GTL  
No. of Bits 18  
Static Current 45  
Rating Catalog  
Technology Family GTLP
SN74GTLPH1612 特性
SN74GTLPH1612 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
74GTLPH1612DGGRE4 ACTIVE -40 to 85 7.65 | 1ku TSSOP (DGG) | 56 2000 | LARGE T&R  
74GTLPH1612DGGRG4 ACTIVE -40 to 85 7.65 | 1ku TSSOP (DGG) | 56 2000 | LARGE T&R  
SN74GTLPH1612DGGR ACTIVE -40 to 85 7.65 | 1ku TSSOP (DGG) | 56 2000 | LARGE T&R  
SN74GTLPH1612 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
74GTLPH1612DGGRE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 74GTLPH1612DGGRE4 74GTLPH1612DGGRE4
74GTLPH1612DGGRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 74GTLPH1612DGGRG4 74GTLPH1612DGGRG4
SN74GTLPH1612DGGR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74GTLPH1612DGGR SN74GTLPH1612DGGR
SN74GTLPH1612 应用技术支持与电子电路设计开发资源下载
  1. SN74GTLPH1612 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器特殊逻辑产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)