SN74LV166A 8 位并联负载移位寄存器

The 'LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V VCC operation.

The 'LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding clear (CLR\) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD\) input. When high, SH/LD\ enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function

SN74LV166A
Technology Family LV-A  
Rating Catalog  
SN74LV166A 特性
SN74LV166A 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74LV166AD ACTIVE 0 to 70 49.90 | 1ku SOIC (DW) | 16 40 | TUBE LV166A
SN74LV166ADE4 ACTIVE 0 to 70 49.90 | 1ku SOIC (DW) | 16 40 | TUBE LV166A
SN74LV166ADG4 ACTIVE 0 to 70 49.90 | 1ku SOIC (DW) | 16 40 | TUBE LV166A
SN74LV166AN ACTIVE 0 to 70 54.90 | 1ku PDIP (N) | 16 15 | TUBE SN74LV166AN
SN74LV166ANE4 ACTIVE 0 to 70 54.90 | 1ku PDIP (N) | 16 15 | TUBE SN74LV166AN
SN74LV166A 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74LV166AD Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74LV166AD SN74LV166AD
SN74LV166ADE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74LV166ADE4 SN74LV166ADE4
SN74LV166ADG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74LV166ADG4 SN74LV166ADG4
SN74LV166AN Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type SN74LV166AN SN74LV166AN
SN74LV166ANE4 Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type SN74LV166ANE4 SN74LV166ANE4
SN74LV166A 应用技术支持与电子电路设计开发资源下载
  1. SN74LV166A 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)