SN74LVC1G373 具有三态输出的单路 D 类锁存器

This single D-type latch is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

While the latch-enable (LE) input is high, the Q output follows the data (D) input. When LE is taken low, the Q output is latched at the logic level set up at the D input.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down

SN74LVC1G373
Pin/Package 6DSBGA, 6SC70, 6SOT-23  
Operating Temperature Range(°C) -40 to 85  
IOL(mA) 32  
IOH(mA) -32  
Input Level CMOS  
Vcc max(V) 5.5  
Technology Family LVC  
Vcc min(V) 1.65  
Approx. Price (US$) 0.13 | 1ku  
Output Level CMOS  
No. of Gates 1  
tpd max(ns) 3.5  
ICC(uA) 10
SN74LVC1G373 特性
SN74LVC1G373 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74LVC1G373DBVR ACTIVE -40 to 85 0.13 | 1ku SOT-23 (DBV) | 6 3000 | LARGE T&R  
SN74LVC1G373DCKR ACTIVE -40 to 85 0.13 | 1ku SC70 (DCK) | 6 3000 | LARGE T&R  
SN74LVC1G373YZPR ACTIVE -40 to 85 0.28 | 1ku DSBGA (YFF) | 6 3000 | LARGE T&R  
SN74LVC1G373 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74LVC1G373DBVR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74LVC1G373DBVR SN74LVC1G373DBVR
SN74LVC1G373DCKR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74LVC1G373DCKR SN74LVC1G373DCKR
SN74LVC1G373YZPR Green (RoHS & no Sb/Br)  SNAGCU  Level-1-260C-UNLIM SN74LVC1G373YZPR SN74LVC1G373YZPR
SN74LVC1G373 应用技术支持与电子电路设计开发资源下载
  1. SN74LVC1G373 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)