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SN74LVC1G74 具有清零和预设功能的单路上升沿 D 类触发器

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down

	SN74LVC1G74
Pin/Package	8DSBGA, 8SM8, 8US8
Operating Temperature Range(°C)	-40 to 85
IOL(mA)	32
IOH(mA)	-32
Input Level	CMOS
Vcc max(V)	5.5
Technology Family	LVC
Vcc min(V)	1.65
Approx. Price (US$)	0.18 | 1ku
Output Level	CMOS
No. of Gates	2
tpd max(ns)	4.4
ICC(uA)	10
Rating	Catalog

SN74LVC1G74 特性

• Available in the Texas Instruments NanoFree™ Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 5.9 ns at 3.3 V
• Low Power Consumption, 10-µA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 1000-V Charged-Device Model (C101)

SN74LVC1G74 芯片订购指南

器件	状态	温度	封装 | 引脚	封装数量 | 封装载体	丝印标记
SN74LVC1G74DCT3	PREVIEW	-40 to 85	SM8 (DCT) | 8	250
SN74LVC1G74DCTR	ACTIVE	-40 to 85	SM8 (DCT) | 8	3000 | LARGE T&R
SN74LVC1G74DCTR-P	PREVIEW	-40 to 85	SM8 (DCT) | 8	3000
SN74LVC1G74DCTRE6	PREVIEW	-40 to 85	SM8 (DCT) | 8	3000
SN74LVC1G74DCU	PREVIEW	-40 to 85	US8 (DCU) | 8	3000
SN74LVC1G74DCU6	PREVIEW	-40 to 85	US8 (DCU) | 8	3000 | LARGE T&R
SN74LVC1G74DCUR	ACTIVE	-40 to 85	US8 (DCU) | 8	3000 | LARGE T&R
SN74LVC1G74DCUR-P	PREVIEW	-40 to 85	US8 (DCU) | 8	3000
SN74LVC1G74DCUT	ACTIVE	-40 to 85	US8 (DCU) | 8	250 | SMALL T&R
SN74LVC1G74YZPR	PREVIEW	-40 to 85	DSBGA (YZP) | 8	3000 | LARGE T&R
SN74LVC1G74YZTR	PREVIEW	-40 to 85	DSBGA (YZT) | 8	3000 | LARGE T&R

SN74LVC1G74 应用技术支持与电子电路设计开发资源下载

1. SN74LVC1G74 数据资料 dataSheet 下载.PDF
2. TI 德州仪器小尺寸逻辑器件产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)