SN74LVTH322374 具有三态输出的 3.3V ABT 32 位边沿触发 D 类触发器

The SN74LVTH322374 is a 32-bit edge-triggered D-type flip-flop with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

This device can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict

SN74LVTH322374
Voltage Nodes(V) 3.3, 2.7  
Vcc range(V) 2.7 to 3.6  
Input Level TTL  
Output Level TTL  
Output Drive(mA) -/+12  
No. of Outputs 32  
No. of Bits 32  
Static Current 10 mA  
th(ns) 0.8  
tpd max(ns) 5.3  
tsu(ns) 1.8  
Logic True  
Technology Family LVT  
Rating Catalog
SN74LVTH322374 特性
SN74LVTH322374 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
74LVTH322374ZKER ACTIVE -40 to 85 2.75 | 1ku LFBGA (GKE) | 96 1000 | LARGE T&R  
SN74LVTH322374KR NRND -40 to 85 2.75 | 1ku LFBGA (GKE) | 96 1000 | LARGE T&R  
SN74LVTH322374 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
74LVTH322374ZKER Green (RoHS & no Sb/Br)  SNAGCU  Level-3-260C-168 HR 74LVTH322374ZKER 74LVTH322374ZKER
SN74LVTH322374KR TBD  SNPB  Level-2-235C-1 YEAR SN74LVTH322374KR SN74LVTH322374KR
SN74LVTH322374 应用技术支持与电子电路设计开发资源下载
  1. SN74LVTH322374 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)