SN74SSTL16837A 具有三态输出的 20 位 SSTL_3 接口通用总线驱动器

This 20-bit universal bus driver is designed for 3-V to 3.6-V VCC operation and SSTL_3 or LVTTL I/O levels.

Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when latch enable (LE) is high. The A data is latched if LE is low and clock (CLK) is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74SSTL16837A is characterized for operation from 0°C to 70°C

SN74SSTL16837A
Voltage Nodes(V) 3.3  
Input Level HSTL  
Output Level LVTTL  
Technology Family HSTL  
Rating Catalog
SN74SSTL16837A 特性
SN74SSTL16837A 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
74HSTL16919DGGRE4 ACTIVE 0 to 70 8.25 | 1ku TSSOP (DGG) | 64 2000 | LARGE T&R  
74HSTL16919DGGRG4 ACTIVE 0 to 70 8.25 | 1ku TSSOP (DGG) | 64 2000 | LARGE T&R  
SN74SSTL16837ADGGR ACTIVE 0 to 70 8.25 | 1ku TSSOP (DGG) | 64 2000 | LARGE T&R  
SN74SSTL16837A 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
74HSTL16919DGGRE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 74HSTL16919DGGRE4 74HSTL16919DGGRE4
74HSTL16919DGGRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 74HSTL16919DGGRG4 74HSTL16919DGGRG4
SN74SSTL16837ADGGR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74SSTL16837ADGGR SN74SSTL16837ADGGR
SN74SSTL16837A 应用技术支持与电子电路设计开发资源下载
  1. SN74SSTL16837A 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器特殊逻辑产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)