SN74SSTU32866A 具有地址奇偶校验测试的 25 位可配置寄存缓冲器

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only 1 device per DIMM is required to drive 9 SDRAM loads. In the 1:2 pinout configuration, 2 devices per DIMM are required to drive 18 SDRAM loads.

All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the open-drain error (QERR) output.

The SN74SSTU32866A buffer operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK\ going low.

The SN74SSTU32866A buffer accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2-D3, D5-D6, D8-D25 when C0 = 0 and C1 = 0; D2-D3, D5-D6, D8-D14 when C0 = 0 and C1=1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low).

SN74SSTU32866A
Voltage Nodes(V) 1.8  
Vcc range(V) 1.7 to 1.9  
Input Level SSTL_18  
Output Level SSTL_18  
Logic True  
No. of Gates 25  
Output Drive(mA) -8/8  
Static Current 50 mA  
tpd max(ns) 2.15  
Technology Family SSTL  
Rating Catalog
SN74SSTU32866A 特性
SN74SSTU32866A 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74SSTU32866AGKER ACTIVE 0 to 70 7.65 | 1ku LFBGA (GKE) | 96 1000 | LARGE T&R  
SN74SSTU32866AZKER ACTIVE 0 to 70 7.65 | 1ku LFBGA (ZKE) | 96 1000 | LARGE T&R  
SN74SSTU32866A 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74SSTU32866AGKER TBD  Call TI  Level-3-220C-168 HR SN74SSTU32866AGKER SN74SSTU32866AGKER
SN74SSTU32866AZKER Green (RoHS & no Sb/Br)  SNAGCU  Level-3-260C-168 HR SN74SSTU32866AZKER SN74SSTU32866AZKER
SN74SSTU32866A 应用技术支持与电子电路设计开发资源下载
  1. SN74SSTU32866A 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器特殊逻辑产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)