ADS808 12 位 70MSPS ADC,具有单端/差动输入、内部/外部参考、灵活时钟、可选择全范围和断电功能

ADS808
Resolution(Bits) 12
Sample Rate (max) 70MSPS
Architecture Pipeline
Power Consumption(Typ)(mW) 720
SINAD(dB) 64
SNR(dB) 64
SFDR(dB) 68
DNL(Max)(+/-LSB) 1.7
INL(Max)(+/-LSB) 4
No Missing Codes(Bits) 12
ENOB(Bits) 0.7
No. of Supplies 2
Analog Voltage AV/DD(Min)(V) 4.75
Analog Voltage AV/DD(Max)(V) 5.25
Logic Voltage DV/DD(Min)(V) 3.0
Logic Voltage DV/DD(Max)(V) 5.0
Input Configuration Range 1V / 2V (p-p)
Reference Mode Int and Ext
Rating Catalog
Pin/Package 48HTQFP
# Input Channels 1

The ADS808 is a high-dynamic range, 12-bit, 70MHz, pipelined Analog-to-Digital Converter (ADC). It includes a high-bandwidth linear track-and-hold that has a low jitter of only 0.25ps rms, leading to excellent SNR performance. The clock input can accept a low-level differential sine wave or square wave signal down to 0.5Vp-p, further improving the SNR performance. It also accepts a single-ended clock signal and has flexible threshold levels.

The ADS808 has a 2Vp-p differential input range (1Vp-p • 2 inputs) for optimum signal-to-noise ratio. The differential operation gives the lowest even-order harmonic components. A lower input voltage of 1.5Vp-p or 1Vp-p can also be selected using the internal references, further optimizing SFDR.

ADS808 特性
ADS808 芯片订购指南
器件 状态 价格(美元) 封装 | 引脚
ADS808Y/250 ACTIVE 26.80 | 1ku HTQFP (PHP) | 48
ADS808Y/250G4 ACTIVE 26.80 | 1ku HTQFP (PHP) | 48
ADS808 应用技术支持与电子电路设计开发资源下载
  1. ADS808 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器仪ADC 模数转换器产品选型与价格 . xls