CD4724B CMOS 8 位可寻址锁存器

CD4724B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.

Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs.

A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level

CD4724B
Voltage Nodes(V) 5, 10, 15  
Rating Military  
Technology Family CD4000
CD4724B 特性
CD4724B 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
CD4724BE ACTIVE -55 to 125 1.25 | 1ku PDIP (N) | 16 25 | TUBE CD4724BE
CD4724BEE4 ACTIVE -55 to 125 1.25 | 1ku PDIP (N) | 16 25 | TUBE CD4724BE
CD4724BPWR ACTIVE -55 to 125 1.20 | 1ku TSSOP (PW) | 16 2000 | LARGE T&R CD4724B
CD4724BPWRE4 ACTIVE -55 to 125 1.20 | 1ku TSSOP (PW) | 16 2000 | LARGE T&R CD4724B
CD4724BPWRG4 ACTIVE -55 to 125 1.20 | 1ku TSSOP (PW) | 16 2000 | LARGE T&R CD4724B
CD4724B 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
CD4724BE Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type CD4724BE CD4724BE
CD4724BEE4 Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type CD4724BEE4 CD4724BEE4
CD4724BPWR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD4724BPWR CD4724BPWR
CD4724BPWRE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD4724BPWRE4 CD4724BPWRE4
CD4724BPWRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD4724BPWRG4 CD4724BPWRG4
CD4724B 应用技术支持与电子电路设计开发资源下载
  1. CD4724B 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)