HMC959LC3 26 GHz, Divide-By-4 SMT with Reset & Programmable Output Voltage
The HMC959LC3 is a Divide-by-4 with Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted, the output toggles from its prior state on the positive edge of the clock. This results in a divide-by-four function of the clock input. Asserting the reset pin forces the Q output low regardless of the clock edge state (asynchronous reset assertion). Reversing the clock inputs allows for negative-edge triggered applications. The HMC959LC3 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization. All input signals to the HMC959LC3 are terminated with 50 Ω to ground on-chip, and may be either AC or DC coupled. Outputs can be connected directly to a 50 Ω terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ω to a non-ground DC voltage. The HMC959LC3 operates from a single -3.3 V DC supply and is available in a ceramic RoHS-compliant 3x3 mm SMT package.
技术特性
- Differential & Singe-Ended Operation
- Fast Rise and Fall Times: 19 ps
- Low Power Consumption: 281 mW typ.
- Programmable Differential Output
Voltage Swing: 800 - 1800 mVp-p
- Propagation Delay: 121 ps
- Single Supply: -3.3V
- 16 Lead 3x3mm SMT Package: 9mm²
订购信息 Ordering Information
应用领域 APPLICATION
- High Speed Frequency Divider
(up to 26 GHz)
- Broadband Test & Measurement
- Clock Synthesis
- Phase Locked Loops
|
技术指标
Data/
Clock Rate (Gbps/GHz) |
Function |
Rise/Fall Time
(ps) |
Diff. Output Swing (Vp-p) |
DC Power Consumption (mW) |
DC Power Supply (Vdc) |
Package |
| - / 26 |
Clock Divide-by-4 |
19 / 19 |
0.8 - 1.8 |
281 |
-3.3 |
LC3 |
功能框图 Functional Block Diagram
|
