ATF750CL PLD可编程逻辑器件

Commercial tpd 15
Generic Part 750
I/O Pins 24,28
Macrocells 10
Power Options LOW
Registers 20
Usable Gates 500
Vcc (V) 5.0
Packages CERDIP 24
LCC 28
Pb-Free Packages TSSOP 24
PDIP 24
PLCC 28
SOIC (300mil) 24

20 FFs, 10 I/O Pins, low power, Vcc-5V, Green package, 750 gates PLD

The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform predictable delays guarantee fast in-system performance. The ATF750C(L) is a high-performance CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes Atmel’s proven electricallyerasable technology. Each of the ATF750C(L)’s 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. There are two sum terms per output, providing added flexibility. A variable format is used to assign between four to eight product terms per sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. The ATF750CL is a low-power device with speeds as fast as 15 ns. The ATF750CL provides the optimum low-power CPLD solution. This device significantly reduces total system power, thereby allowing battery-powered operations.

ATF750CL 特征
ATF750CL 订货型号
Devices tPD
(ns)
tCOS
(ns)
Ext.
fMAXS
(MHz)
Ordering Code Package Operation Range
ATF750C 10 7 83 ATF750C-10JU
ATF750C-10PU
ATF750C-10SU
ATF750C-10XU
28J
24P3
24S
24X
Industrial (-40°C to 85°C)
ATF750CL 15 10 44 ATF750CL-15JU
ATF750CL-15PU
ATF750CL-15SU
ATF750CL-15XU
28J
24P3
24S
24X
ATF750CL 应用技术支持与电子电路设计开发资源下载
  1. ATMEL 爱特梅尔PLD可编程逻辑器件ATF750CL 数据手册Da0taSheet 下载.PDF
  2. ATMEL 产品选型目录. PDF
  3. 相关SPLD / CPLD 可编程逻辑选型表
  4. Atmel PLDs' Architectures Simplify Timing Calculations . pdf (4 pages, updated 8/99)
    This Application Note shows different graphical timing models that can help the user visualize the AC timing of the various Atmel PLD families of devices.
  5. Saving Power with Atmel PLDs . pdf (7 pages, updated 9/00)
    This Application Note is is a detailed description and explanation of the Atmel Input Transition Detection "L" Feature
  6. Using a PLD as a System Controller in an I/O Bus Based System . pdf (7 pages, updated 9/99)
    As Programmable Logic Devices (PLDs) become more complex, the amount of logic that can be placed in one device is rapidly increasing. Complete controllers and subsystems now fit into one or two PLDs.
  7. Using the ATV750 and ATV750B . pdf(13 pages, updated 9/99)
    This Application Note describes how to use the features of the ATV750 and ATV750B in the ABEL (and Atmel-ABEL) and CUPL (and Atmel-CUPL) high level description languages.
  8. Migrating from ATV750B/BL to ATF750C/CL . pdf (6 pages, updated 9/08)
    This Application Note will assist customers in migrating from the ATV750B/BL PLDs to the ATF750C/CL.