74LVC2G17GV: 双路非反相施密特触发器,带5 V容压输入

74LVC2G17提供两个带施密特触发器输入的非反相缓冲器。该器件能够将缓慢变化的输入信号转换成清晰无抖动的输出信号。

输入可通过3.3 V或5 V器件进行驱动。该特性允许在混合3.3 V和5 V环境中将这些器件用作转换器。

该器件完全适合使用IOFF的局部掉电应用。IOFF电路可禁用输出,防止掉电时破坏性回流电流通过该器件。

74LVC2G17GV: 产品结构框图
SOT457
数据手册 (1)
名称/描述Modified Date
Dual non-inverting Schmitt trigger with 5 V tolerant input (REV 8.0) PDF (200.0 kB) 74LVC2G17 [English]02 May 2013
应用说明 (4)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]04 Feb 2011
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
封装信息 (1)
名称/描述Modified Date
plastic surface-mounted package (TSOP6); 6 leads (REV 1.0) PDF (248.0 kB) SOT457 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (187.0 kB) SOT457_125 [English]30 Nov 2012
支持信息 (3)
名称/描述Modified Date
Reflow Soldering Profile (REV 1.0) PDF (34.0 kB) REFLOW_SOLDERING_PROFILE [English]30 Sep 2013
Wave Soldering Profile (REV 1.0) PDF (20.0 kB) WAVE_SOLDERING_PROFILE [English]30 Sep 2013
MAR_SOT457 Topmark (REV 1.0) PDF (113.0 kB) MAR_SOT457 [English]03 Jun 2013
IBIS
订购信息
型号状态Family功能VCC (V)说明Logic switching levelsOutput drive capability (mA)Package versiontpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVC2G17GVActiveLVCSchmitt-triggers1.65 - 5.5dual buffer Schmitt-triggerCMOS/LVTTL+/- 32SOT4573.61752low-40~12523239.4145TSOP66
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74LVC2G17GVSOT457Reflow_Soldering_Profile Wave_Soldering_Profile
Reflow_Soldering_Profile Wave_Soldering_Profile
Reel 7" Q3/T4, ReverseActive74LVC2G17GV,125 (9352 733 19125)Standard Marking74LVC2G17GVAlways Pb-free123.83.872.58E811
Dual non-inverting Schmitt trigger with 5 V tolerant input 74LVC2G17GW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Pin FMEA for LVC family 74LVC1G123_Q100
PicoGate Logic footprints NX3L4684
MAR_SOT457 Topmark 74LVC2G17_Q100
74LVC2G17 IBIS model 74LVC2G17GW
plastic surface-mounted package (TSOP6); 6 leads 74LVC2G17_Q100
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
Reflow_Soldering_Profile Wave_Soldering_Profile LPC1112FD20
Tape reel SMD; reversed product orientation 12NC ending 125 74LVC2G17_Q100
74LVC2G17
SSL5021_SSL5031