ADF4193 Low Phase Noise, Fast Settling PLL Frequency Synthesizer

The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).

The Σ-Δ-based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures.

Applications
  • GSM/EDGE base stations
  • PHS base stations
  • Instrumentation and test equipment
Features and Benefits
  • New, fast settling, fractional-N PLL architecture
  • Single PLL replaces ping-pong synthesizers
  • Frequency hop across GSM band in 5 µs with phase settled by 20 µs
  • 0.5° rms phase error at 2 GHz RF output
  • Digitally programmable output phase
  • RF input range up to 3.5 GHz
  • 3-wire serial interface
  • On-chip, low noise differential amplifier
  • Phase noise figure of merit: –216 dBc/Hz
  • Loop filter design possible using ADIsimPLL™
  • Qualified for automotive applications
  • RF & Microwave
    Data Sheets
    Documentnote
    ADF4193: Low Phase Noise, Fast Settling PLL Frequency Synthesizer Data Sheet (Rev. G)PDF 584 kB
    Application Notes
    Documentnote
    AN-0974: Multicarrier TD-SCMA FeasibilityPDF 634 kB
    AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)PDF 207 kB
    User Guides
    Documentnote
    UG-476: PLL Software Installation GuidePDF 520 kB
    UG-536: Evaluating the ADF4193 and ADF4196 Frequency Synthesizers for Phase-Locked LoopsPDF 443 kB
    Frequently Asked Questions
    Documentnote
    Order Information
    Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
    ADF4193BCPZ Production32 ld LFCSP (5x5mm) w/3.1mm exposed padOTH 490-40 to 85C5.514.88Y
    ADF4193BCPZ-RL Production32 ld LFCSP (5x5mm) w/3.1mm exposed padREEL 5000-40 to 85C00Y
    ADF4193BCPZ-RL7 Production32 ld LFCSP (5x5mm) w/3.1mm exposed padREEL 1500-40 to 85C04.88Y
    ADF4193WCCPZ-RL7 Production32 ld LFCSP (5x5mm) w/3.1mm exposed padREEL 1500-40 to 105C07.5Y
    Evaluation Boards
    Part NumberDescriptionPriceRoHS
    EV-ADF4193SD1ZEvaluation board with 1.8 GHz VCO and loop filter components populated165Y
    EV-ADF4193SD2ZEvaluation board without VCO or loop filter components140Y
    EVAL-SDP-CS1ZSDP-S Controller Board - Interface to EV-ADF4193SD1Z and EV-ADF4193SD2Z (also required)49Y
    Reference Materials
    ADF4193: Low Phase Noise, Fast Settling PLL Frequency Synthesizer Data Sheet (Rev. G) adf4193
    AN-0974: Multicarrier TD-SCMA Feasibility ad6655
    AN-0974: TD-SCMA多载波系统可行性研究 (Rev. 0) ad8376
    AN-873: ADF4xxx系列PLL频率合成器的锁定检测 (Rev. 0) ad9540
    AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0) ad9540
    UG-476: PLL Software Installation Guide adf9010
    UG-476:PLL软件安装指南 adf4360-1
    UG-536: Evaluating the ADF4193 and ADF4196 Frequency Synthesizers for Phase-Locked Loops adf4193
    RF Source Booklet adf9010