74ALVCH32973EC: 16-bit bus transceiver and transparant D-type latch with 8 independent buffers

The 74ALVCH32973 is a 16-bit bus transceiver and transparent D-type latch with 8 independent buffers with bus hold inputs and 3-state outputs. It features direction (1DIR, 2DIR), latch enable (1LOE, 2LOE), transceiver output enable (1TOE, 2TOE) and latch enable (1LE, 2LE) control inputs; four 8-bit transceiver ports (1An, 2An & 1Bn, 2Bn); two 8-bit D-type latch output ports (1Qn, 2Qn) and an 8-bit buffer with data inputs Dn and outputs Yn. The configuration of the control pins allows the device to be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one 16-bit transceiver and one 16-bit latch.

The 8-bit buffer functions independently of the control inputs. The direction of data transmission between A and B is controlled by nDIR and when nTOE is set HIGH the A and B ports will assume a HIGH-impedance OFF-state, they will be effectively isolated. When nLE is HIGH, data at the A inputs enter the latches. In this condition the latches are transparent, a Q output will change each time its corresponding A-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nLOE causes the Q outputs to assume a high-impedance OFF-state. Operation of the nLOE input does not affect the state of the latches.

74ALVCH32973EC: Product Block Diagram

sot536-1_3d

Data Sheets (1)

Name/Description	Modified Date
16-bit bus transceiver and transparant D-type latch with 8 independent buffers (REV 3.0) PDF (176.0 kB) 74ALVCH32973 [English]	17 Jan 2013

Application Notes (7)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
(LF)BGA Application note, ATO Innovation (REV 1.0) PDF (69.0 kB) AN1026_1 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English]	13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]	13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013
ANLFBGA 32-Bit Logic Families in Low-profile Fine-pitch Ball Grid Array (LFBGA) Packages (REV 1.0) PDF (453.0 kB) ANLFBGA [English]	13 Mar 2013

Brochures (3)

Name/Description	Modified Date
Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English]	10 Jul 2015
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm (REV 1.0) PDF (438.0 kB) SOT536-1 [English]	08 Feb 2016

Ordering Information

Product	Status	Family	Function	V_CC (V)	Logic switching levels	Description	Output drive capability (mA)	Package version	t_pd (ns)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74ALVCH32973EC	Active	ALVC	Latches/registered drivers	1.8 - 3.6	LVTTL	16-bit transceiver and transparent D-type latch with 8 independent buffers	+/- 24	SOT536-1	2.5	16	low	-40~85	60	16.0		LFBGA96	96