MC100EPT23: Translator, Dual Differential LVPECL to LVTTL
The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for applications which require the translation of a clock and a data signal.The EPT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the EPT23 does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the MC100EPT23 can accept any standard differential LVPECL input referenced from a VCC of +3.3V.
特性
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封装
应用注释 (18)
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 3.3 V Dual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator | MC100EPT23/D (157kB) | 19 | Aug, 2016 |
仿真模型 (4)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| EPT21/23/25 ECLinPS PlusE Translator TTL output SPICE Modeling Kit | AND8118/D (53.0kB) | 0 | |
| IBIS Model for mc100ept23mn 3.3 V | MC100EPT23MN_33.IBS (7.0kB) | 1 | |
| IBS Model for MC100EPT23D 3.3V | MC100EPT23D_33.IBS (7.0kB) | 3 | |
| IBS Model for MC100EPT23DT | MC100EPT23DT_33.IBS (7.0kB) | 3 |
封装图纸 (3)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| DFN8 2.0x2.0x0.9mm, 0.5p | 506AA (31.8kB) | F |
| SOIC-8 Narrow Body | 751-07 (62.6kB) | AK |
| TSSOP 8 3.0x3.0x0.95 mm | 948R-02 (77.3kB) | A |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC100EPT23DG | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tube | 98 | 联系BDTIC |
| MC100EPT23DR2G | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tape and Reel | 2500 | 联系BDTIC |
| MC100EPT23DTG | Active | Pb-free Halide free | TSSOP-8 | 948R-02 | 3 | Tube | 100 | 联系BDTIC |
| MC100EPT23DTR2G | Active | Pb-free Halide free | TSSOP-8 | 948R-02 | 3 | Tape and Reel | 2500 | 联系BDTIC |
| MC100EPT23MNR4G | Active | Pb-free Halide free | DFN-8 | 506AA | 1 | Tape and Reel | 1000 | 联系BDTIC |
订购产品技术参数
| Product | Channels | Input Level | Output Level | VCC Typ (V) | fMax Typ (MHz) | tpd Typ (ns) | tR & tF Max (ps) |
|---|---|---|---|---|---|---|---|
| MC100EPT23DG | 2 | ECL LVDS CML | TTL | 3.3 | 350 | 1.5 | 900 |
| MC100EPT23DR2G | 2 | CML LVDS ECL | TTL | 3.3 | 350 | 1.5 | 900 |
| MC100EPT23DTG | 2 | CML ECL LVDS | TTL | 3.3 | 350 | 1.5 | 900 |
| MC100EPT23DTR2G | 2 | LVDS ECL CML | TTL | 3.3 | 350 | 1.5 | 900 |
| MC100EPT23MNR4G | 2 | CML ECL LVDS | TTL | 3.3 | 350 | 1.5 | 900 |
- AC Characteristics of ECL Devices NB100LVEP91
- Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS Plus™ Spice Modeling Kit MC10EPT20
- ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
- EPT Spice Modeling Kit MC10EPT20
- Interfacing Between LVDS and ECL NB100ELT23L
- Interfacing with ECLinPS NB100LVEP91
- Metastability and the ECLinPS Family MC10EPT20
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Phase Lock Loop General Operations MC10H604
- Storage and Handling of Drypack Surface Mount Device NB3U23C
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
- EPT21/23/25 ECLinPS PlusE Translator TTL output SPICE Modeling Kit MC100EPT25
- IBIS Model for mc100ept23mn 3.3 V MC100EPT23
- IBS Model for MC100EPT23D 3.3V MC100EPT23
- IBS Model for MC100EPT23DT MC100EPT23
- SOIC-8 Narrow Body CM1216
- TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
- DFN8 2.0x2.0x0.9mm, 0.5p NUF4220
