CD74HC112 具有设置和复位功能的高速 CMOS 逻辑双路下降沿 J-K 触发器

The ’HC112 and ’HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, Set, Reset, and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Set and Reset are accomplished asynchronously by low-level inputs.

The HCT logic family is functionally as well as pin-compatible with the standard LS logic family

CD74HC112
Technology Family HC
Rating Catalog  
CD74HC112 特性
CD74HC112 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
CD74HC112E ACTIVE -55 to 125 0.34 | 1ku PDIP (N) | 14 25 | TUBE CD74HC112E
CD74HC112EE4 ACTIVE -55 to 125 0.34 | 1ku PDIP (N) | 14 25 | TUBE CD74HC112E
CD74HC112M96 ACTIVE -55 to 125 0.31 | 1ku SOIC (D) | 14 2500 | LARGE T&R HC112M
CD74HC112M96E4 ACTIVE -55 to 125 0.31 | 1ku SOIC (D) | 14 2500 | LARGE T&R HC112M
CD74HC112M96G4 ACTIVE -55 to 125 0.31 | 1ku SOIC (D) | 14 2500 | LARGE T&R HC112M
CD74HC112 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
CD74HC112E Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type CD74HC112E CD74HC112E
CD74HC112EE4 Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type CD74HC112EE4 CD74HC112EE4
CD74HC112M96 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD74HC112M96 CD74HC112M96
CD74HC112M96E4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD74HC112M96E4 CD74HC112M96E4
CD74HC112M96G4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM CD74HC112M96G4 CD74HC112M96G4
CD74HC112 应用技术支持与电子电路设计开发资源下载
  1. CD74HC112 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)