TLC3544CPW 14 位、5V、200KSPS、4 通道单级性 ADC封装TSSOP-20

TLC3544
Resolution(Bits) 14
Sample Rate (max) 200kSPS
Architecture SAR
Power Consumption(Typ)(mW) 20
SINAD(dB) 81
SNR(dB) 81
SFDR(dB) 97
DNL(Max)(+/-LSB) 1
INL(Max)(+/-LSB) 1
No Missing Codes(Bits) 14
No. of Supplies 2
Analog Voltage AV/DD(Min)(V) 4.5
Analog Voltage AV/DD(Max)(V) 5.5
Logic Voltage DV/DD(Min)(V) 2.7
Logic Voltage DV/DD(Max)(V) 5.5
Input Configuration Range +4V
Reference Mode Int and Ext
Rating Catalog
Pin/Package 20SOIC, 20TSSOP
# Input Channels 4
Operating Temp Range(Celsius) -40 to 85,0 to 70 

The TLC3544 and TLC3548 are a family of 14-bit resolution high-performance, low-power, CMOS analog-to-digital converters (ADC). All devices operate from a single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital inputs [chip select (CS\), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS\ (works as SS\, slave select), SDI, SDO, and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form a DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS\ works as the chip select to allow the host DSP to access the individual converter.

TLC3544CPW 特性
TLC3544CPW 芯片订购指南
器件 状态 温度 (oC) 价格(美元) 封装 | 引脚
TLC3544CDW ACTIVE 0 to 70 7.50 | 1ku SOIC (DW) | 20
TLC3544CDWG4 ACTIVE 0 to 70 7.50 | 1ku SOIC (DW) | 20
TLC3544CPW ACTIVE 0 to 70 8.30 | 1ku TSSOP (PW) | 20
TLC3544CPWG4 ACTIVE 0 to 70 8.30 | 1ku TSSOP (PW) | 20
TLC3544CPWR ACTIVE 0 to 70 7.50 | 1ku TSSOP (PW) | 20
TLC3544CPWRG4 ACTIVE 0 to 70 7.50 | 1ku TSSOP (PW) | 20
TLC3544IDW ACTIVE -40 to 85 8.10 | 1ku SOIC (DW) | 20
TLC3544IDWG4 ACTIVE -40 to 85 8.10 | 1ku SOIC (DW) | 20
TLC3544IPW ACTIVE -40 to 85 8.10 | 1ku TSSOP (PW) | 20
TLC3544IPWG4 ACTIVE -40 to 85 8.10 | 1ku TSSOP (PW) | 20
TLC3544CPW 应用技术支持与电子电路设计开发资源下载
  1. TLC3544CPW 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器仪ADC 模数转换器产品选型与价格 . xls