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CD74HC4518 高速 CMOS 逻辑双路 BCD 加计数器

The CD74HC4518 is a dual BCD up-counter. The ’HC4520 and CD74HCT4520 are dual binary up-counters. Each device consists of two independent internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or the negative-going transition of CLOCK. The counters are cleared by high levels on the MASTER RESET lines. The counter can be cascaded in the ripple mode by connecting Q3 to the ENABLE input of the subsequent counter while the CLOCK input of the latter is held low.

	CD74HC4518
Rating	Catalog
Technology Family	HC

CD74HC4518 特性

• Positive or Negative Edge Triggering
• Synchronous Internal Carry Propagation
• Fanout (Over Temperature Range)
  • Standard Outputs...10 LSTTL Loads
  • Bus Driver Outputs...15 LSTTL Loads
• Wide Operating Temperature Range... –55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
  • 2V to 6V Operation
  • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
  • CMOS Input Compatibility, Il 1µA at VOL, VOH

CD74HC4518 芯片订购指南

器件	状态	温度	价格	封装 | 引脚	封装数量 | 封装载体	丝印标记
CD74HC4518E	ACTIVE	-55 to 125	0.39 | 1ku	PDIP (N) | 16	25 | TUBE
CD74HC4518EE4	ACTIVE	-55 to 125	0.39 | 1ku	PDIP (N) | 16	25 | TUBE

CD74HC4518 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
CD74HC4518E	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	CD74HC4518E	CD74HC4518E
CD74HC4518EE4	Pb-Free (RoHS)	CU NIPDAU	N/A for Pkg Type	CD74HC4518EE4	CD74HC4518EE4

CD74HC4518 应用技术支持与电子电路设计开发资源下载

1. CD74HC4518 数据资料 dataSheet 下载.PDF
2. TI 德州仪器MSI 功能产品选型与价格 . xls
3. Logic Guide 2009 (PDF 4263 KB)
4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
9. Designing With Logic (PDF 186 KB)
10. Live Insertion (PDF 150 KB)
11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
14. LOGIC Pocket Data Book (PDF 6001 KB)
15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
16. Logic Cross-Reference (PDF 2938 KB)