SN74AS867 同步 8 位加/减计数器

These synchronous, presettable, 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (,) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform.

These counters are fully programmable; they may be preset to any number between 0 and 255. The load-input circuitry allows parallel loading of the cascaded counters

SN74AS867
Rating Catalog  
Technology Family AS
SN74AS867 特性
SN74AS867 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74AS867DW ACTIVE 0 to 70 3.55 | 1ku SOIC(DW) | 24 2000 | LARGE T&R  
SN74AS867DWE4 ACTIVE 0 to 70 3.55 | 1ku SOIC(DW) | 24 2000 | LARGE T&R  
SN74AS867DWG4 ACTIVE 0 to 70 3.55 | 1ku SOIC(DW) | 24 2000 | LARGE T&R  
SN74AS867N ACTIVE 0 to 70 3.90 | 1ku PDIP (N) | 20 20 | TUBE  
SN74AS867NE4 ACTIVE 0 to 70 3.90 | 1ku PDIP (N) | 20 20 | TUBE  
SN74AS867 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74AS867DW Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74AS867DW SN74AS867DW
SN74AS867DWE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74AS867DWE4 SN74AS867DWE4
SN74AS867DWG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74AS867DWG4 SN74AS867DWG4
SN74AS867N Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type SN74AS867N SN74AS867N
SN74AS867NE4 Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type SN74AS867NE4 SN74AS867NE4
SN74AS867 应用技术支持与电子电路设计开发资源下载
  1. SN74AS867 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器MSI 功能产品选型与价格 . xls
  3. Logic Guide 2009 (PDF 4263 KB)
  4. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  9. Designing With Logic (PDF 186 KB)
  10. Live Insertion (PDF 150 KB)
  11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  14. LOGIC Pocket Data Book (PDF 6001 KB)
  15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  16. Logic Cross-Reference (PDF 2938 KB)