SN74GTL3004 可选 GTL 电压基准

The SN74GTL3004 provides for a selectable GTL Voltage Reference (GTL VREF). The value of the GTL VREF can be adjusted using S0 and S1 select pins.

The S0 and S1 pins contain glitch-suppression circuitry for excellent noise immunity. When left floating, the S0 and S1 control input pins have 100-kµ pullups that set the GTL VREF default value to the 0.67 × VTT ratio (S0 = 1 and S1 =1).

SN74GTL3004
No. of Outputs 1  
Vcc range(V) 3 to 3.6  
Operating Temperature Range(°C) -40 to 85  
Pin/Package 6SC70  
Technology Family GTL
SN74GTL3004 特性
SN74GTL3004 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74GTL3004DCKR ACTIVE -40 to 85 0.33 | 1ku SC70 (DCK) | 6 3000 | LARGE T&R  
SN74GTL3004DCKRG4 ACTIVE -40 to 85 0.33 | 1ku SC70 (DCK) | 6 3000 | LARGE T&R  
SN74GTL3004 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74GTL3004DCKR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74GTL3004DCKR SN74GTL3004DCKR
SN74GTL3004DCKRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74GTL3004DCKRG4 SN74GTL3004DCKRG4
SN74GTL3004 应用技术支持与电子电路设计开发资源下载
  1. SN74GTL3004 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器电压电平转换产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)